Characterizing state devices for switching noise

Greater processing power has given rise to modern EDA tools which allow detailed analog analysis of ASIC power distribution networks. Switching noise can now be accurately simulated and monitored throughout the I/O rings and core electronics. These EDA tools can generate warning messages when simulated switching noise values exceed user-specified maximum acceptable levels. Unfortunately, maximum allowable switching noise is not accurately approximated based on V_IL levels, V _IH levels, and gate switching speed. This study determines the sensitivity of state devices (flip-flops and latches) to switching noise using a simulation-based approach and the 0.8 micron CMOSX standard cell library. Sensitivities to noise on clock and asynchronous inputs are characterized in terms of switching voltage and pulse duration. Maximum allowable noise levels are presented for many CMOSX state devices. Also, two conclusions were reached: (1) acceptable levels of switching noise may vary greatly between state devices and (2) minor design changes may greatly improve susceptibility to switching noise