Key technologies for 500-MHz VLSI system ULTIMATE

Author

Tamama, Teruo ; Narumi, Naoaki ; Otsuji, Tai-Ichi ; Suzuki, Masao ; Sudo, Tsuneta

Author_Institution

LSI Lab., NTT, Kanagawa, Japan

fYear

1988

fDate

12-14 Sep 1988

Firstpage

108

Lastpage

113

Abstract

Technologies needed for constructing ULTIMATE, including an 8-ps-resolution timing generator, a formatter with a real-time waveform control function, a 2.5-ps-resolution standard comparator, and a miniaturized 3-GHz 59-pole channel selector are described. Almost all the pin-electronics hardware has been integrated on twelve kinds of LSIs, eight of which are 2.5 K-gate and 400-gate ultrahigh-speed bipolar gate arrays. ULTIMATE realizes ±55-ps overall timing accuracy by the timing calibration method which combines a standard comparator-based method and a TDR (time-domain reflectometry)-based method

Keywords

VLSI; automatic test equipment; automatic testing; integrated circuit testing; logic arrays; logic testing; reflectometers; time-domain reflectometry; 3 GHz; 500 MHz; 59-pole channel selector; ATE; ULTIMATE; VLSI; formatter; logic arrays; logic testing; pin-electronics hardware; real-time waveform control function; standard comparator; time-domain reflectometry; timing calibration; timing generator; ultrahigh speed testing; ultrahigh-speed bipolar gate arrays; Accuracy; Capacitance; Capacitors; Circuit testing; Delay effects; Inverters; Large scale integration; Matrix converters; Timing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1988. Proceedings. New Frontiers in Testing, International

Conference_Location

Washington, DC

ISSN

1089-3539

Print_ISBN

0-8186-0870-6

Type

conf

DOI

10.1109/TEST.1988.207787

Filename

207787