Title :
A bit-level systolic 2D-IIR digital filter without feedback
Author :
Hu, Zhijian ; Gaston, Fiona
Author_Institution :
Dept. of Electron. & Electr. Eng., Birmingham Univ., UK
Abstract :
This paper addresses the implementation aspect of a high performance bit-level systolic 2D IIR digital filter. A new data input scheme is used to solve the basic problem of latency in the feedback loop. The resulting design has increased parallelism and regularity. The simple modular structure leads to an efficient VLSI implementation. The filter has a throughput rate of one sample every clock cycle, which is twice that of previous published implementations.
Keywords :
CMOS digital integrated circuits; IIR filters; VLSI; modules; pipeline processing; recursive filters; systolic arrays; two-dimensional digital filters; 2-D recursive filtering; CMOS technology; VLSI implementation; bit level systolic 2D-IIR digital filter; clock cycle; data input; feedback loop latency; image processing; modular structure; parallel design; pipelined arrays; regular design; throughput rate; Circuits; Clocks; Delay; Digital filters; Equations; Feedback loop; Finite impulse response filter; Hardware; IIR filters; Pipeline processing;
Conference_Titel :
Signals, Systems and Computers, 1996. Conference Record of the Thirtieth Asilomar Conference on
Conference_Location :
Pacific Grove, CA, USA
Print_ISBN :
0-8186-7646-9
DOI :
10.1109/ACSSC.1996.599106
