Title :
G-RIDDLE: a formal analysis of logic designs conducive to the acceleration of backtracing
Author :
Silberman, Gabriel M. ; Spillinger, Ilan
Author_Institution :
Technion, Israel Inst. of Technol., Haifa, Israel
Abstract :
A formal approach to the analysis of combinatorial gate-level designs is presented which produces information conducive to the acceleration of test generation algorithms. This analysis yields, as its main product, information which can be used to reduce the amount of effort expended during backtracing by guiding this process towards decision (assignments) less likely to cause conflicts and by minimizing the amount of work between backtracks. The G-RIDDLE approach is introduced for performing this analysis, as a refinement of the more general case which handles designs consisting of multi-input/multioutput combinatorial blocks. Experimental results are given for a popular benchmark of combinatorial gate-level designs
Keywords :
VLSI; combinatorial circuits; integrated circuit testing; integrated logic circuits; logic CAD; logic testing; G-RIDDLE; VLSI; backtracing; benchmark; combinatorial gate-level designs; logic CAD; logic designs; logic testing; test generation algorithms; Acceleration; Algorithm design and analysis; Benchmark testing; Circuit testing; Computer science; Information analysis; Logic design; Performance analysis; Test pattern generators; Very large scale integration;
Conference_Titel :
Test Conference, 1988. Proceedings. New Frontiers in Testing, International
Conference_Location :
Washington, DC
Print_ISBN :
0-8186-0870-6
DOI :
10.1109/TEST.1988.207863
