Title :
A simulation study of CMOS performance improvement by laser annealed source/drain extension profiles
Author :
Axelrad, Valery ; Al-Bayati, Amir ; Adibi, Babak ; Carey, Paul
Author_Institution :
SEQUOIA Design Syst., Woodside, CA, USA
Abstract :
Laser thermal processing (LTP) dramatically changes the feasibility of ultra shallow and highly doped source-drain extensions (SDE). In comparison to conventional rapid thermal processing (RTP) profiles, steeper profiles and higher peak concentrations are achieved. This is of particular importance for sub-100 nm devices, where limited steepness of RTP profiles can result in significant source-drain resistance (Rsd) and severe short-channel effects. In this work we demonstrate that LTP technologies can reduce the source/drain resistance Rsd by more than 70% for Lpoly below 100 nm in both NMOS and PMOS. This leads to increases in saturation currents by up to 10%. Significant improvements in very deep submicron MOSFET performance can thus be expected as a result of this new technology being deployed
Keywords :
CMOS integrated circuits; MOSFET; ion implantation; laser beam annealing; CMOS performance; Lpoly; NMOS; PMOS; RTP profiles; laser annealed source/drain extension profiles; laser thermal processing; saturation currents; short-channel effects; simulation; source-drain resistance; sub-100 nm devices; very deep submicron MOSFET performance; CMOS process; CMOS technology; FETs; Implants; Laser transitions; MOS devices; Optical design; Rapid thermal processing; Simulated annealing; Thermal resistance;
Conference_Titel :
Ion Implantation Technology, 2000. Conference on
Conference_Location :
Alpbach
Print_ISBN :
0-7803-6462-7
DOI :
10.1109/.2000.924134