Title :
A routing concept for large sea-of-gates designs
Author :
Bartholomeus, M. ; Weisenseel, W.
Author_Institution :
Siemens AG, Munich, Germany
fDate :
29 May-1 Jun 1990
Abstract :
Sea-of-gates (SoG) is becoming a very important design style for ASICs. Due to a larger flexibility in placement and routing, SoG can achieve higher densities and gate count than conventional gate arrays. Ion this paper the authors describe a routing environment and a routing methodology utilizing all features of this new design style, aiming to automatically complete a large design with high gate utilization, zero uncompleted routing connections with reasonable CPU-resources. In general, this problem cannot be solved with a single algorithm. Rather, a sequence of algorithms which are hierarchical and/or optimized to perform specialized tasks are used
Keywords :
application specific integrated circuits; circuit layout CAD; logic CAD; logic arrays; ASICs; IC routeing; channelless gate arrays; circuit layout; gate arrays; high gate utilization; large SOG designs; routing; sea-of-gates; Algorithm design and analysis; Amplitude shift keying; Degradation; Integrated circuit interconnections; Logic gates; Macrocell networks; Routing; Signal design; Silicon; Topology;
Conference_Titel :
Euro ASIC '90
Conference_Location :
Paris
Print_ISBN :
0-8186-2066-8
DOI :
10.1109/EASIC.1990.207944