DocumentCode
3116041
Title
Parallel electronic circuit simulation on the iPSC system
Author
Yuan, Chen-Ping ; Lucas, Robert ; Chan, Philip ; Dutton, Robert
Author_Institution
Intel Co., Santa Clara, CA, USA
fYear
1988
fDate
16-19 May 1988
Abstract
A parallel circuit simulator was implemented on the iPSC system. Concurrent model evaluation, hierarchical BBDF (bordered block diagonal form) reordering, and distributed multifrontal decomposition to solve the sparse matrix are used. A speedup of six times has been achieved on an eight-processor iPSC hypercube system
Keywords
VLSI; circuit analysis computing; parallel processing; Intel; VLSI; bordered block diagonal form; distributed multifrontal decomposition; hierarchical reordering; hypercube system; iPSC system; parallel circuit simulator; sparse matrix; Circuit simulation; Computational modeling; DH-HEMTs; Electronic circuits; Finite difference methods; Hypercubes; Message passing; Particle separators; Partitioning algorithms; Sparse matrices;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988
Conference_Location
Rochester, NY
Type
conf
DOI
10.1109/CICC.1988.20812
Filename
20812
Link To Document