Title :
A 1.5 V CMOS current-mode cyclic analog-to-digital converter with digital error correction
Author :
Chen, Chih-Cheng ; Wu, Chung-Yu ; Cho, Jyh-Jer
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fDate :
30 Apr-3 May 1995
Abstract :
A new cyclic Analog-to-Digital conversion algorithm with embedded digital error correction is proposed to reduce the linearity errors caused by the comparator inaccuracy and the offset of the S/H operations. New low-voltage fully-balanced current-mode circuits performing the sample/hold, signal-amplification, and current comparison functions are developed to realize a low-voltage current-mode cyclic Analog-to-Digital converter (ADC). With 1.5 V supply voltage and 0.8 μm CMOS device parameters, the HSPICE simulation results show that the designed ADC can achieve 12-bit resolution at 10 k/s conversion rate with the power dissipation of the analog circuits less than 2 mW
Keywords :
CMOS integrated circuits; SPICE; analogue-digital conversion; circuit analysis computing; cyclic codes; digital simulation; sample and hold circuits; 0.8 micron; 1.5 V; 2 mW; CMOS; HSPICE simulation; S/H operations; comparator inaccuracy; conversion rate; current comparison functions; current-mode cyclic analog-to-digital converter; embedded digital error correction; linearity errors; power dissipation; resolution; Analog circuits; Analog-digital conversion; CMOS analog integrated circuits; Circuit simulation; Current mode circuits; Error correction; Linearity; Power dissipation; Signal resolution; Voltage;
Conference_Titel :
Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
0-7803-2570-2
DOI :
10.1109/ISCAS.1995.521569
