An efficient method for custom integrated circuit global routing

The author presents an efficient global routing technique for a custom IC. The router uses a slicing-tree floorplan representation, and wiring is assumed to lie in channels between the modules. Special features of the router are: each terminal pin of a net can be specified to be on one of the four boundaries or at the center of a module (if a boundary location is unknown); a mapping of terminal pins to module corner to reduce the graph complexity; the use of four `imaginary modules´ bounding the IC to facilitate computations using the arcs on the boundary of the IC; and options to reroute each net a specified number of times and update routing costs after any specified number of nets have been routed. The author provides a comparative study of CPU time/area/wirelength for various rerouting and cost updating strategies, in particular comparing sequential one-pass routing vs. independent (e.g. parallel) rerouting