Automatic synthesis of signal processing benchmark using the CATHEDRAL silicon compilers

A discussion is presented of implementation of two WDF (wave digital filter) benchmarks that have been designed with three architecture-specific silicon compilers. The design time for high-level synthesis and optimization is roughly one day. For each of the three synthesis systems, the elapsed design cycle starting from the specifications down to the optimized signal flow graph is another 1-2 days. For the architecture and layout generation (including the evaluation of the tradeoffs), the design time ranges from a few hours to a day. Specific higher-level filter specifications have been used for the synthesis with three different implementation strategies in the CATHEDRAL silicon compilers. It is shown that as an initial optimization step, it is important to initially choose a good algorithm