Title :
Hardware requirements of communication-centric machine learning algorithms
Author :
Koskinen, Lauri ; Roverato, Enrico
Author_Institution :
Dept. of Micro & Nanosci., Aalto Univ., Aalto, Finland
Abstract :
Machine learning type neuromorphic algorithms have the potential to enable the brains behind small autonomous robots, provided these algorithms can be implemented energy efficiently. The implementation difficulties are mainly extremely large memory size and high memory bandwidth making Von Neumann computational model realizations inefficient. However, these algorithms are inherently error robust, which may be taken advantage of in the realizations. For example, in with low operating voltage stochastic hardware. To determine the hardware requirements for an Application Specific Integrated Circuit (ASIC) realization, an example algorithm, Hierarchical Temporal Memory (HTM), is realized here. A 64×64 HTM network with 1440 connections per elementary processing element requires 530 mm2 area, 340 Mb memory, and a 10MHz clock frequency in 65nm technology. With point-to-point connections these processing elements would have a communication radius of circa 50 elements and on-chip wideband technologies can increase the range further.
Keywords :
application specific integrated circuits; learning (artificial intelligence); neural nets; ASIC realization; HTM; Von Neumann computational model; application specific integrated circuit; communication-centric machine learning algorithm; frequency 10 MHz; hierarchical temporal memory; machine learning type neuromorphic algorithm; point-to-point connection; size 65 nm; Algorithm design and analysis; Hardware; Machine learning algorithms; Memory management; Microprocessors; Neuromorphics; Adaptive systems; Machine Learning; Parallel processing;
Conference_Titel :
Adaptive Hardware and Systems (AHS), 2013 NASA/ESA Conference on
Conference_Location :
Torino
DOI :
10.1109/AHS.2013.6604237