DocumentCode
3124591
Title
A 10-bit 5 Msample/sec CMOS 2-step flash ADC
Author
Doernberg, Joey ; Hodges, David A.
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fYear
1988
fDate
16-19 May 1988
Abstract
A 10-bit, 5-Msample/s, two-step flash A/D (analog-to-digital) converter fabricated in a 1.6-μm CMOS process is described. With minimal capacitor-matching requirements and comparator offset-voltage cancellation, the architecture is monotonic. To minimize charge-injection errors, the converter is fully differential. A high-speed comparator architecture using three comparator stages was designed to provide a gain of more than 1000 and a comparison time of less than 10 ns. The total area of the converter excluding the bonding pads is 54k square mils. Power dissipation is 350 mW, of which 60 mW is dissipated in the resistor string
Keywords
CMOS integrated circuits; analogue-digital conversion; 1.6 micron; 10 bit; 10 ns; 2-step flash ADC; 350 mW; A/D convertor; CMOS process; charge-injection errors; comparison time; high-speed comparator architecture; Application specific integrated circuits; Capacitors; Diodes; Feedback loop; Latches; Power dissipation; Sampling methods; Switches; Testing; Transconductance;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988
Conference_Location
Rochester, NY
Type
conf
DOI
10.1109/CICC.1988.20894
Filename
20894
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