Translation from DEVS models to synthesizable VHDL programs

This paper proposes a new approach to the development of VLSI systems. DEVS (Discrete EVent System Specification) formalism specifies discrete event systems in a hierarchical, modular form. This formalism provides clear and sound semantics to describe complex VLSI systems. We are using the formalism for the functional verification and the performance evaluation of a real DSP processor. Now we use the formalism in describing models, which have enough information to be synthesized. Then the DEVS models are translated into synthesizable VHDL programs. This method provides several advantages over the previous approach that starts a system description with VHDL. Using DEVS formalism allows designers to concentrate on the dynamics of a target system. The formalism provides an efficient simulation framework. We can apply formal verification without any additional annotation or annoying mathematical notation. A well-defined model management methodology is also provided. These advantages make the increasing design complexity of VLSI systems more manageable and the productivity of development higher