Signal Processing Domain Application Mapping on the Brick Reconfigurable Array

This paper introduces the proposal of an expression grain reconfigurable architecture called BRICK, its functionality and main components. A mapping for three signal processing applications such as a 3×3 2-D convolution, a 16-tap FIR filter and an 8-point FFT is developed inside the 4×4 reconfigurable array. A performance simulation analysis study is developed comparing the BRICK reconfigurable array VHDL implementation to a MIPS and a SPARC V8 simulators in order to validate the reconfigurable array proposal. Considerable gains up to an order of magnitude are obtained and important design issues and challenges were discovered when developing this work.