DocumentCode :
3129302
Title :
A Pipelined Program Decompression Engine Generator Based on Partial Field-Partitioned (PFP) Compression Technique for Embedded Systems
Author :
Jeang, Yuan-Long ; Hu, Ko-Yen
Author_Institution :
Dept. of Inf. Eng., Kun Shan Univ., Yung-Kang, Taiwan
fYear :
2010
fDate :
15-17 Oct. 2010
Firstpage :
296
Lastpage :
299
Abstract :
For rare instructions, the decompression cost is higher than the saving due to compression. This paper presents a new technique, called partial field partitioned compressing so that some rare instructions are field-partitioned into smaller parts and then, compress these parts in the same field to reduce the cost. A software program has been designed to generate a Verilog (a Hardware Description Language) description of a decompression engine for each compressed ARM program. Then, the description is synthesized using Design Compiler of the Synopsys Co. The synthesized results for several benchmarks show that all cases are better than the results of our previous versions.
Keywords :
embedded systems; hardware description languages; Verilog; compressed ARM program; design compiler; embedded system; hardware description language; partial field-partitioned compression; pipelined program decompression engine generator; software program; Benchmark testing; Decoding; Detectors; Embedded systems; Engines; Program processors; VLIW;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP), 2010 Sixth International Conference on
Conference_Location :
Darmstadt
Print_ISBN :
978-1-4244-8378-5
Electronic_ISBN :
978-0-7695-4222-5
Type :
conf
DOI :
10.1109/IIHMSP.2010.81
Filename :
5638034
Link To Document :
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