DocumentCode
3129372
Title
A functional FinFET-DGCMOS SRAM cell
Author
Nowak, E.J. ; Rainey, B.A. ; Fried, D.M. ; Kedzierski, J. ; Ieong, M. ; Leipold, W. ; Wright, J. ; Breitwisch, M.
Author_Institution
IBM Corp., Essex Junction, VT, USA
fYear
2002
fDate
8-11 Dec. 2002
Firstpage
411
Lastpage
414
Abstract
An operational six-transistor SRAM cell is experimentally demonstrated using Double Gate CMOS FinFET technology. A cell size of 4.8 /spl mu/m/sup 2/ was achieved in 180 nm node technology, with stable operation at 1.5 V using a single level of copper interconnect. To our knowledge this represents the first experimental demonstration of a fully integrated FinFET SRAM Cell.
Keywords
CMOS memory circuits; SRAM chips; circuit stability; integrated circuit interconnections; integrated circuit layout; 1.5 V; 180 nm; 180 nm node technology; Cu; butterfly curves; cell size; double gate CMOS FinFET technology; functional FinFET-DGCMOS SRAM cell; planar-cell layout; single level copper interconnect; six-transistor SRAM cell; stable operation; CMOS technology; Copper; Etching; FinFETs; Integrated circuit interconnections; Inverters; MOSFETs; Oxidation; Random access memory; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 2002. IEDM '02. International
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-7803-7462-2
Type
conf
DOI
10.1109/IEDM.2002.1175866
Filename
1175866
Link To Document