Title :
A capacitorless double-gate DRAM cell design for high density applications
Author :
Kuo, C. ; Tsu-Jae King ; Chenming Hu
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Abstract :
Experimental measurements and 2-D device simulation are used to investigate a capacitorless, asymmetric double-gate DRAM (DG-DRAM) design. Soft error problems are discussed. Careful attention to cell geometry and film quality results in intrinsic retention times suitable for stand-alone and embedded memories.
Keywords :
CMOS memory circuits; DRAM chips; MOSFET; integrated circuit design; radiation hardening (electronics); silicon-on-insulator; 2-D device simulation; CMOS memory technologies; capacitorless asymmetric double-gate DRAM design; capacitorless double-gate DRAM cell design; cell geometry; embedded memories; film quality; fully depleted SOI MOSFET; high density applications; intrinsic retention times; recessed channel SOI process; soft error problems; stand-alone memories; Back; Capacitors; Doping profiles; MOSFET circuits; Random access memory; Semiconductor films; Silicon; Substrates; Threshold voltage; Tunneling;
Conference_Titel :
Electron Devices Meeting, 2002. IEDM '02. International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7462-2
DOI :
10.1109/IEDM.2002.1175969
