Modular silicon-on-insulator process for power devices and power integrated circuits

Summary form only given. Power semiconductors suffer from eroding market prices, while shrinking feature size offers limited potential for die size reduction, due to fundamental semiconductor electric field limitations. Efforts have thus recently concentrated on fundamentally different device construction (RESURF rather than vertical DMOS) or novel materials that permit higher electric fields (Weitzel, 1998). This work presents the ramp-up to volume production of a thin-film silicon-on-insulator (TFSOI) process in a volume manufacturing line. This process, originally conceived in our research labs in Briarcliff (Letavic et al., 1997), permits integration of up to 850 V devices with record-breaking on-resistance together with protection and control circuits. In order to respond optimally to customer requirements, the process can be modified in a modular way to adapt to voltage requirements, digital content complexity, need for complementary power devices, and need for high-side (related to positive supply) CMOS circuitry. The most important modular variants are an 11-mask 650 V process, a 14-mask 850 V process with complementary power devices, and a 16-mask process providing full CMOS discrete power components. The paper demonstrates the physics that allows lower on-resistance with this novel technology and presents the modular process architecture. We give an overview of the issues encountered in transferring the process to a volume production environment (plasma processing, metrology), and address some SOI specific issues (latch-up prevention, heat dissipation, ESD performance, high temperature operation)