Electrical integrity of state-of-the-art 0.13 /spl mu/m SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication

Author

Guarini, K.W. ; Topol, A.W. ; Ieong, M. ; Yu, R. ; Shi, L. ; Newport, M.R. ; Frank, D.J. ; Singh, D.V. ; Cohen, G.M. ; Nitta, S.V. ; Boyd, D.C. ; Neil, P. A Å ; Tempest, S.L. ; Pogge, H.B. ; Purushothaman, S. ; Haensch, W.E.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

2002

fDate

8-11 Dec. 2002

Firstpage

943

Lastpage

945

Abstract

We introduce a new scheme for building three-dimensional (3D) integrated circuits (ICs) based on the layer transfer of completed devices. We demonstrate for the first time that the processes required for stacking active device layers preserve the intrinsic electrical characteristics of state-of-the-art short-channel MOSFETs and ring oscillator circuits, which is critical to the success of high performance 3D ICs.

Keywords

CMOS integrated circuits; MOSFET; integrated circuit technology; silicon-on-insulator; 0.13 micron; SOI CMOS circuit; SOI CMOS device; active device layer stacking; electrical characteristics; electrical integrity; layer transfer; ring oscillator; short-channel MOSFET; three-dimensional integrated circuit fabrication; CMOS integrated circuits; CMOS technology; Circuit testing; Fabrication; Glass; Integrated circuit interconnections; Metallization; Ring oscillators; Substrates; Three-dimensional integrated circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2002. IEDM '02. International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-7462-2

Type

conf

DOI

10.1109/IEDM.2002.1175992

Filename

1175992