DocumentCode :
3132084
Title :
10-MB/s multi-level programming of Gb-scale flash memory enabled by new AG-AND cell technology
Author :
Sasago, Y. ; Arigane, T. ; Kurata, H. ; Saeki, S. ; Goto, Y. ; Kamohara, S. ; Kobayashi, T. ; Kume, H.
Author_Institution :
Central Res. Lab., Hitachi Ltd., Kokubunji, Japan
fYear :
2002
fDate :
8-11 Dec. 2002
Firstpage :
952
Lastpage :
954
Abstract :
This paper describes the first exhaustive study of a multi-level flash memory cell that achieves a programming throughput of over 10 MB/s. We reveal that increasing the individual cell programming speed (2 /spl mu/s), reducing the distribution in cell programming speeds (1.2 V), and reducing the inter-floating gate coupling to reduce Vth shift (0.15 V) are required. These three specifications are achieved by a new AG-AND cell technology consisting of self-aligned isolated punch-through stopper (SAIPTS) and U-shaped floating. This results in multilevel programming faster than 10 MB/s for the first time.
Keywords :
PLD programming; flash memories; 10 MB/s; 10-MB/s multi-level programming; 2 mus; Gb-scale flash memory; U-shaped floating; assist-gate AND cell technology; cell programming speed distribution reducing; individual cell programming speed; inter-floating gate coupling; multi-level flash memory; programming throughput; self-aligned isolated punch-through stopper; threshold voltage shift; Electronic mail; Flash memory; Flash memory cells; Isolation technology; Laboratories; Nonvolatile memory; Paper technology; Threshold voltage; Throughput; Tunneling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting, 2002. IEDM '02. International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7462-2
Type :
conf
DOI :
10.1109/IEDM.2002.1175995
Filename :
1175995
Link To Document :
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