DocumentCode
3132855
Title
The effects of cache architecture on the performance of operating systems in multithreaded processors
Author
Lioupis, Dimitris ; Milios, Sotiris
Author_Institution
Comput. Technol. Inst., Patras, Greece
fYear
1997
fDate
11-13 Jun 1997
Firstpage
72
Lastpage
79
Abstract
Multithreading is well accepted as a technique to hide latency in non-blocking cache architectures. By switching execution from a blocked thread to another, the CPU can perform useful work, while waiting for long requests to be processed by the memory hierarchy. In this paper we study four memory hierarchy organizations, and we find that the performance of the operating system, in terms of response time, greatly depends on the cache configuration and memory hierarchy. For a simple cache design, the OS response time can be below 50%, which can only be improved by increasing the cache size or associativity. We find that the best way to guarantee OS response time in multithreaded processors is to use pipelined memory, which reduces the miss penalty and thus the uncertainty in response time
Keywords
cache storage; memory architecture; multiprogramming; operating systems (computers); pipeline processing; software performance evaluation; CPU; associativity; blocked thread; cache architecture; cache configuration; cache design; latency; memory hierarchy organizations; miss penalty; multithreaded processors; operating systems performance; pipelined memory; response time; Aggregates; Computer architecture; Computer networks; Data engineering; Delay; Multiprocessor interconnection networks; Multithreading; Operating systems; Throughput; Yarn;
fLanguage
English
Publisher
ieee
Conference_Titel
Real-Time Systems, 1997. Proceedings., Ninth Euromicro Workshop on
Conference_Location
Toledo
Print_ISBN
0-8186-8034-2
Type
conf
DOI
10.1109/EMWRTS.1997.613766
Filename
613766
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