Energy efficient on-chip wireless interconnects with sleepy transceivers

Both industry and academia has accepted Networks-on-Chip (NoCs) as the communication backbone for multi-core Systems-on-Chip (SoCs). But the traditional approach of implementing a NoC with planar metal interconnects has high latency and significant power consumption overhead. This is due to multi-hop links used in data exchange, specifically when the number of cores is significantly high. To address these problems multi-hop wire interconnects in a NoC can be replaced with high-bandwidth single-hop long-range wireless links. This opens up new opportunities for detailed investigations into the energy efficient design of wireless NoCs using suitable on-chip wireless transceivers. Wireless transceivers with power gating can significantly improve the energy efficiency of the interconnection network. In this paper we have implemented and evaluated sleep transistor based power-gated transceiver for low power on-chip wireless interconnects. This approach improved power saving for wireless communication up to 70% compared to existing wireless NoC. The transceiver consumes 36.8771 mA current while on and less than 9 nA while in sleep mode from 1 V power supply. The delay associated with this wireless transceiver is less than 10 ps.