Title :
Case study: effectiveness of high-speed scan based feed forward voltage testing in reducing DPPM on a high volume ASIC
Author :
Lurkins, Joel ; Hill, Deanna ; Benware, Brady
Author_Institution :
LSI Logic Corp.
Abstract :
A case study implementing the reduced vector set feed forward minimum voltage (RVSFF MinVDD) defect screening method on a high volume 0.18mum ASIC is presented. RVSFF MinVDD outliers from a high speed transition delay fault (TDF) scan test were identified and exercised in high temperature operating life (HTOL), and then monitored on automatic test equipment (ATE) and functional circuit test (FCT) to help determine the impact on early failure rate (EFR) and shipped product quality level (SPQL). Defective parts per million (DPPM) improvements are evaluated under two conditions, 1) IDDQ outlier screening already exists at ATE and MinVDD outlier screening is added, and 2) MinVDD is the only outlier screen that has been implemented. The results indicate that an EFR improvement of approximately 100 DPPM is achieved with the implementation of the MinVDD outlier screen
Keywords :
application specific integrated circuits; automatic test equipment; boundary scan testing; built-in self test; delays; integrated circuit testing; logic testing; 0.18 micron; ASIC; automatic test equipment; feed forward voltage testing; functional circuit test; high temperature operating life; high-speed scan testing; screening method; shipped product quality level; transition delay fault; Application specific integrated circuits; Automatic testing; Circuit faults; Circuit testing; Delay; Fault diagnosis; Feeds; Life testing; Temperature; Voltage;
Conference_Titel :
Test Conference, 2005. Proceedings. ITC 2005. IEEE International
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-9038-5
DOI :
10.1109/TEST.2005.1584090
