The concern for soft errors is not overblown

Single event upsets in logic paths are an emerging concern for computing systems built in advanced CMOS technologies. Upset rates for latches used in sequential circuits are increasing, and combinatorial circuit elements will also become a factor for future technology nodes. Each transient event has a potential for manifesting into a fault, or, less likely but much more serious, an undetected error. Improvement in understanding, mitigation techniques, and accurate models from technology to system level are required to manage SER in the future