Hardware-assisted simulation and evaluation of IP cores using FPGA-based rapid prototyping boards

This paper presents a methodology for incorporating intellectual property (IP) cores that are implemented with SRAM-based FPGA logic into an existing hardware simulation environment for functional simulation and evaluation purposes, using a simple serial communication interface based on the IEEE 1149.1 standard (also known as JTAG) with minimal hardware requirements. We also describe a prototype software/hardware implementation of the proposed approach and present a case study to demonstrate the feasibility of our approach.