SystemC model of a MPEG-2 DVB-T bit-rate measurement architecture for FPGA implementation

The SystemC description language is used to model and simulate a digital hardware design in order to speed up its development. In this paper, we present the development of a real time bit-rate architecture for digital television data stream. The bit rate measurement of a digital program stream is one among other metrics of the quality of service (QoS) of a DVB transport Stream. This paper presents an electronic architecture tailored to the real time measurement of the bit rate of a MPEG2-DVB-T program. This architecture follows the standard published by the ETSI and has been modelled and validated by mean of the SystemC language. This model also allows to define implementation constraints and shows that the architecture can be entirely implemented in a FPGA with the help of a SystemC-VHDL translator.