A Peak Detector for Multi-Rate Phase Locked Loop and Sequence Detector Combination for Utility AC Power Applications

Synchronization is of concern in AC power systems. Existing synchronization algorithms are hardware intensive. A single phase synchronization scheme referred to as a multi-rate phase locked loop (MPLL) has been reported. The stability of the MPLL is influenced by amplitude variations. An amplitude estimation module based on a fast Fourier transform (FFT) algorithm and an automatic gain control (AGC) are employed to decouple amplitude variations from phase variations. The implementation of the FFT-based amplitude-estimator is complex and hardware intensive. A peak detector module that utilizes only two multiplexers and one comparator is proposed to replace the FFT-based amplitude-estimator. A real-time positive sequence detector is also combined with the MPLL in order to allow process of the three-phase signals. The overall system is implemented and compared for both FFT-based and peak detector approaches and indicates a 60 dB immunity to impulse noise and harmonic contamination and a 20 dB dynamic range