Steady state and transient thermal analysis of hot spots in 3D stacked ICs using dedicated test chips

3D stacking of dies is a promising technique to allow miniaturization and performance enhancement of electronic systems. The complexity of the interconnection structures, combined with the reduced thermal spreading in the thinned dies and the poorly thermally conductive adhesives complicate the thermal behavior of a stacked die structure. The same dissipation will lead to higher temperatures and a more pronounced temperature peak in a stacked die package compared to a single die package. Therefore, the thermal behavior in a 3D-IC needs to be studied thoroughly. In this paper, a steady state and transient analysis is presented for hot spots in 3D stacked structures. For this analysis, dedicated test chips with integrated heaters and temperature sensors are used to assess the temperature profile in the different tiers of the stack and to investigate the impact of TSVs on the temperature profile. This experimental set-up is used to evaluated and improve the thermal models for the 3D stacks.