Finite element modeling of a back grinding process for Through Silicon Vias

The optimization of grinding parameters for silicon wafers is necessary in order to maximize the reliability of electronic packages. This paper describes the work performed to simulate a back grinding process for Through Silicon Via (TSV) wafers using the commercial finite element code ABAQUS. The grinding of a TSV silicon wafer with a thickness of 120 μm mounted on a backing tape was simulated. The wafer was thinned to a thickness of 115.5 μm, by simulating the grinding with a diamond particle cutting through successive silicon and copper layers. The computed residual stresses induced in the wafer were compared with experimental values, and the plastic deformation in the simulated ground surface was compared with literature data and showed good correlation. The numerical model developed can be used to better understand the local grinding parameters in the TSV wafers and the effect of the of the copper vias on the wafer properties.