Repeater Sizing and Insertion Length of Interconnect to Minimize the Overall Time Delay using a Truncated Fourier Series Approach

Computation of accurate time domain signal waveforms in VLSI interconnects, taking into account the distributed inductance of the line, has grown in importance with increasing clock speeds. A computationally efficient truncated Fourier series method for computing time domain waveforms is summarized in this work. The method assumes excitation of the VLSI interconnect modeled in the frequency domain, by periodic trapezoidal waveforms. The problem of optimizing repeater size and interconnect insertion length to minimize time delay in long interconnects, taking into account the transmission line nature of the interconnect using this Fourier series method is developed in this work. The Nelder-Mead simplex optimization technique is used to perform the actual optimizations. At each step of the Nelder-Mead iteration, the candidate interconnect length and repeater scaling at that iteration is used to evaluate the output time response using the truncated Fourier series. The results of the optimization by this method are compared with that obtained by a fourth-order Fade approximation based optimization technique in the literature. The results of the two optimization studies show significant differences in overall optimized time delay per meter. The differences are attributable to the error in the Fade approximation of the transfer function of the interconnect and terminations