VLSI implementation for a low power mobile OFDM receiver ASIC

An OFDM receiver ASIC specifically targeting mobile applications has been designed and fabricated. The receiver ASIC incorporates the digital front-end receiver, pre/post-FFT processing units, a 1024-point complex (I)FFT processor, channel estimator and corrector, all digital synchronization loops, and control and configuration interface. In this paper we describe the VLSI implementation and optimization for the ASIC that entails a compact design with low power dissipation. Finite-precision effects are analyzed to minimize the computation requirements for major signal processing blocks. Performance and implementation cost tradeoff on time/frequency synchronization and channel estimation are also analyzed. The final receiver ASIC dissipates only 32 mW while providing a date-rate of 8 Mb/s (uncoded) in highspeed mobile environments, making the chip suitable for packet-based mobile applications.