Logic Design Automation of MOS Combinational Networks with Fan-In, Fan-Out Constraints

With the increasing complexity of current digital systems, many aspects have to be considered in the Logic design of these systems. Among them are the pin limitations, interconnections, power dissipation, testability, and fan-in, fan-out constraints. Since MOS (metal oxide semiconductor) is playing a major role in large scal integration (LSI), the problem of synthesis of MOS switching networks with large number of variables is very important. The main advantage of MOS over other forms of integrated circuits is the possibility of obtaining higher chip logic density. Long propagation delay limits MOS to low speed applications, however, speed can be improved by using advanced types of MOS as VMOS, DMOS and HMOS. An efficient algorithm for computer-aided synthesis of MOS combinational logic networks was presented in the 1977 Design Automation Conference. That algorithm considered some of the aspects need to be considered in the logic design process. These were pin limitations, interconnections, and testability. In this paper we present a new algorithm which incorporates, in addition to the aspects considered above, the fan-in, fan-out constraints. Designing digital systems with fan-in, fan-out constraints is vital for achieving proper operation of these systems - specifically speed and noise margin. A step-by-step description as well as a detailed synthesis example are given. Some of the steps of this algorithm were programmed in FORTRAN V on a SPERRY UNIVACTM 1108 computer. The effects of this kind of design on the network performance and testability are discussed. Finally, some future research problems in this area are presented.