Title :
LORES - Logic Reorganization System
Author :
Nakamura, Shunjchiro ; Murai, Shinichi ; Tanaka, Chiyoji ; Terai, Masayuki ; Fujiwara, Hideo ; Kinoshita, Kozo
Author_Institution :
Mitsubishi Electric Corp., Kamakura, Japan
Abstract :
Described is the outline and the experimental results of the system which automatically restructures and partitions a logic circuit consisting of standard SSI´s and MSI´s so that the gate types and the numbers of input/output terminals of the reorganized circuits are within the restrictions of the specified LSI.
Keywords :
Circuit simulation; Clocks; Costs; Data mining; Debugging; Large scale integration; Logic arrays; Logic circuits; Logic design; Logic devices;
Conference_Titel :
Design Automation, 1978. 15th Conference on
DOI :
10.1109/DAC.1978.1585181
