Computation of fixed-coefficient inner products over finite rings with the use of pass-transistor networks

This paper presents new designs of fixed-coefficient inner product circuits for finite-ring arithmetic. These circuits are crucial for residue number system (RNS) based digital signal processing (DSP) systems, where computations can often be decomposed to the inner product form. The approach proposed is based on pass-transistor networks and one-hot data representation. Hardware complexity of the new circuits has been analyzed showing that substantial hardware savings can be achieved, compared to implementations based on the bit-sliced inner product step processor (BIPSP/sub m/). A low-cost double-edge-triggered data register has been developed for the new inner product circuits which can also be used in various other pipelined designs.