Optimized power trace numbers in CPA attacks

Author

Benhadjyoussef, Noura ; Machhout, Mohsen ; Tourki, Rached

Author_Institution

Electron. & Micro-Electron. Lab. (E. μ. E. L), Fac. of Sci. of Monastir, Monastir, Tunisia

fYear

2011

fDate

22-25 March 2011

Firstpage

1

Lastpage

5

Abstract

Correlation power analysis is the well-known attack against cryptographic modules. An attacker exploits the correlation between the power consumed by a device and the data being processed. In the present paper, we present the experimental procedure of correlation power analysis using three different devices: FPGA, ASIC and a microcontroller. Results show that the power model used to calculate hypothetical power is related to the algorithm and not to the platform and its validity depends statistically on the implementation.

Keywords

application specific integrated circuits; cryptography; field programmable gate arrays; microcontrollers; statistical analysis; ASIC; CPA attacks; FPGA; correlation power analysis; cryptographic modules; microcontroller; power trace number optimization; Correlation; Cryptography; Field programmable gate arrays; Hardware; Power demand; Power measurement; Software; Advanced Encryption Standard (AES); Correlation power analysis (CPA); Data Encryption Standard (DES); Security; correlation coefficient;

fLanguage

English

Publisher

ieee

Conference_Titel

Systems, Signals and Devices (SSD), 2011 8th International Multi-Conference on

Conference_Location

Sousse

Print_ISBN

978-1-4577-0413-0

Type

conf

DOI

10.1109/SSD.2011.5767431

Filename

5767431