Title :
VLSI testing and test power
Author_Institution :
Dept. of Comput. Syst. & Eng., Kyushu Inst. of Technol., Iizuka, Japan
Abstract :
This paper first reviews the basics of VLSI testing, focusing on test generation and design for testability. Then it discusses the impact of test power in scan testing, and highlights the need for low-power VLSI testing.
Keywords :
VLSI; low-power VLSI testing; scan testing; test generation; test power; Circuit faults; Clocks; Delay; Integrated circuit modeling; Sequential circuits; Testing; Very large scale integration; VLSI testing; at-speed scan testing; capture power; design for testability; low-power testing; scan design; scan testing; shift power; test generation; test power;
Conference_Titel :
Green Computing Conference and Workshops (IGCC), 2011 International
Conference_Location :
Orlando, FL
Print_ISBN :
978-1-4577-1222-7
DOI :
10.1109/IGCC.2011.6008607
