High-quality physical designs of CMOS ICs

The authors describe a methodology for the assessment and enhancement of the physical testability of CMOS digital ICs, and to present a set of testability design rules to avoid ´difficult to detect´ faults, especially open faults. The methodology and the design rules are used in the development of a high-quality, highly testable cell library. A design example is presented, which ascertains the usefulness of the approach, and the achievable gains in testability, reliability and eventually in yield.<>