Title :
An ASIC for image dilation and erosion
Author :
Baatour, M. ; Rampon, J. ; Tertre, Y.
Author_Institution :
Inst. Nat. Polytech. de Grenoble, CSI, France
Abstract :
A VLSI chip to compute two morphological operations, dilation and erosion, over discrete black and white images is presented here. The chip contains 96 PEs organized as a 12*8 2D array of processing elements (PEs) performing in an SIMD mode. Each PE is connected to its four neighbors.<>
Keywords :
VLSI; application specific integrated circuits; image processing; microprocessor chips; parallel processing; special purpose computers; 2D array of processing elements; ASIC; Eurochip; SIMD mode; VLSI chip; black and white images; image dilation; image erosion; morphological operations; Application specific integrated circuits; Image enhancement; Morphological operations; Nearest neighbor searches; Noise reduction; Pixel; Process design; Registers; Very large scale integration;
Conference_Titel :
Euro ASIC '91
Conference_Location :
Paris, France
Print_ISBN :
0-8186-2185-0
DOI :
10.1109/EUASIC.1991.212857
