Study on multi-channel receiver based on polyphase filter bank

Author

Iwabuchi, Masashi ; Sakaguchi, Kei ; Araki, Kiyomichi

Author_Institution

Dept. of Electr. & Electron. Eng., Tokyo Inst. of Technol., Tokyo

fYear

2008

fDate

15-17 Dec. 2008

Firstpage

1

Lastpage

7

Abstract

Recently, mutli-channel aggregation has been considered, e.q. in IEEE 802.20 (MBTDD 625 k-MC mode), to achieve higher throughput on legacy wireless systems. To realize such a system, a multi-channel digital down converter (DDC) is needed for the receiver. In a conventional scheme, parallel DDCs are used to implement the mutli-channel DDC. However, such architecture results in a high computational cost. In this paper, a new circuit architecture for multi-channel DDC based on a polyphase filter and DFT filter bank is studied. By using the proposed architecture, the number of multipliers (the circuit size) can be reduced significantly compared with the conventional mutli-channel DDC while maintaining power consumption.

Keywords

channel bank filters; convertors; radio receivers; wireless channels; digital down converter; legacy wireless system; multichannel receiver; multipliers; polyphase filter bank; power consumption; Filter bank;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing and Communication Systems, 2008. ICSPCS 2008. 2nd International Conference on

Conference_Location

Gold Coast, QLD

Print_ISBN

978-1-4244-4243-0

Electronic_ISBN

978-1-4244-4243-0

Type

conf

DOI

10.1109/ICSPCS.2008.4813691

Filename

4813691