VHDL in logic synthesis-an applications perspective

Shows some aspects of VHDL for synthesis (and simulation) from a very practical view. One of the aspects addressed is the integration of VHDL into current design flows with respect to the need of graphical interfaces. A synthesis example shows the advantage of VHDL to facilitate the specification of the structure of a block´s architecture together with its functional description. Comparisons to other means of circuit specification show its expressiveness to cover all practical applications. This gives an estimation of the necessary efforts to port already existing circuit models into VHDL.<>