A SIMD machine for beamforming on a chip

Author

Giacalone, J.-P. ; Del Gallo, Y.

Author_Institution

Thomson Sintra ASM, Sophia-Antipolis, France

fYear

1991

fDate

27-31 May 1991

Firstpage

41

Lastpage

44

Abstract

A CMOS integrated circuit containing 400000 transistors was produced to implement a beamforming algorithm. Using an SIMD architecture, it implements two pipelined 24-bits floating point multiply-accumulate units, developing a total computing power of 64 Mflops for a 60-ns cycle time. This circuit is controlled by a micro-sequencer which manages an external memory of two Mwords (24-bits instructions and data), simultaneously accessing four data elements. Designed for use in a parallel machine environment, it has a built-in communication manager.<>

Keywords

CMOS integrated circuits; application specific integrated circuits; digital signal processing chips; parallel architectures; sonar; 24 bits; 60 ns; 64 MFLOPS; CMOS integrated circuit; SIMD architecture; beamforming; built-in communication manager; cycle time; data elements; external memory; floating point multiply-accumulate units; micro-sequencer; parallel machine environment; pipeline processing; Array signal processing; Circuits; Communication system control; Delay effects; Filtering; Finite impulse response filter; Interpolation; Memory management; Signal processing; Signal processing algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Euro ASIC '91

Conference_Location

Paris, France

Print_ISBN

0-8186-2185-0

Type

conf

DOI

10.1109/EUASIC.1991.212897

Filename

212897