DocumentCode :
3140833
Title :
A Study on the Floating-Point Adder in FPGAS
Author :
Malik, Ali ; Ko, Seok-Bum
Author_Institution :
Dept. of Electr. Eng., Saskatchewan Univ., Saskatoon, Sask.
fYear :
2006
fDate :
38838
Firstpage :
86
Lastpage :
89
Abstract :
FPAGs are increasingly being used to design high-end computationally intense microprocessors capable of handling both fixed and floating-point mathematical operations. Addition is the most complex operation in a floating-point unit and offers major delay while taking significant area. Over the years, the VLSI community has developed many floating-point adder algorithms mainly aimed to reduce the overall latency. An efficient design of floating-point adder onto an FPGA offers major area and performance overheads. With the recent advancement in FPGA architecture and area density, latency has been the main focus of attention in order to improve performance. Our research was oriented towards studying and implementing standard, LOP, and far and close data-path floating-point addition algorithms. Each algorithm has complex sub-operations which lead significantly to overall latency of the design. Each of the sub-operation is researched for different implementations and then synthesized onto a Xilinx Virtex2p FPGA device to be chosen for best performance. According to our results, standard algorithm is the best implementation with respect to area but has overall large latency of 27.059 ns while occupying 541 slices. LOP algorithm improves latency by 6.5% on added expense of 38% area compared to standard algorithm. Far and close data-path implementation shows 19% improvement in latency on added expense of 88% in area compared to standard algorithm
Keywords :
adders; field programmable gate arrays; floating point arithmetic; logic design; FPGA architecture; LOP algorithm; VLSI community; Xilinx Virtex2p FPGA device; floating-point adder; microprocesor design; Adders; Algorithm design and analysis; Computer architecture; Delay; Field programmable gate arrays; Floating-point arithmetic; Hardware; Microprocessors; Throughput; Very large scale integration; Floating-point Addition;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrical and Computer Engineering, 2006. CCECE '06. Canadian Conference on
Conference_Location :
Ottawa, Ont.
Print_ISBN :
1-4244-0038-4
Electronic_ISBN :
1-4244-0038-4
Type :
conf
DOI :
10.1109/CCECE.2006.277498
Filename :
4054889
Link To Document :
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