Title :
Optimization of the PLA Area
Author_Institution :
Laboratoire IMAG, GRENOBLE, FRANCE
Abstract :
A method to reduce the area of the PLA´s is presented. Two steps are considered : the permutation of the minterms (columns) and the compacting of the PLA. The method is illustrated on the NMOS technology.
Keywords :
Minterm permutation; PLA folding; connection; line merge; peak function; Aluminum; Circuits; Design automation; Inverters; Joining processes; MOS devices; Merging; Programmable logic arrays; Very large scale integration; Minterm permutation; PLA folding; connection; line merge; peak function;
Conference_Titel :
Design Automation, 1981. 18th Conference on
DOI :
10.1109/DAC.1981.1585388
