Bandwidth Expansion in Sigma-Delta PLLs Using Multiphase VCOs

A 120MHz fractional-N frequency synthesizer was implemented in a standard 0.18mum CMOS process with an on-chip multiphase voltage-controlled oscillator (VCO). The proposed architecture uses multiphase outputs of the VCO to decrease quantization noise from the sigma-delta (SigmaDelta) modulator. Results show 6dB decrease in quantization noise for every two fold increase in the number of phases, which allows increase in loop bandwidth. The VCO phase noise was measured to be -104dBc/Hz at 200kHz offset. The loop bandwidth can be increased to 700kHz and still maintain in-band quantization noise below -100dBc/Hz. The power consumption of the synthesizer is 5.4mW with a 1.8V supply and it occupies an active area of 750mum times 550mum. The intended application is subharmonic injection higher frequency VCO and as a clock generator in a subsampling analog-to-digital converter (ADC)