Analysis and Design of a 10 Gbps Transimpedance Amplifier using 0.18μm CMOS technology

This paper examines the design of a 10 Gbps transimpedance amplifier (TIA) in 0.18 mum CMOS technology. In order to compensate for the high parasitic capacitances in the CMOS process, this design uses a shunt and series inductive peaking technique to achieve the required transimpedance bandwidth. A noise analysis on the input stage of the TIA is shown. This noise model is used to determine the optimum device size required to minimize the average input referred noise current. Simulation results for the TIA are presented showing a transimpedance gain of approximately 52 dBΩ. The simulated average input referred noise current of the differential TIA is shown to be approximately 27 pA/√radicHz