Design Verification System for Large-Scale LSI Designs

This paper describes the changing environment of large-scale computer designs as they are influenced by the advance of technology. This changing environment makes it necessary for design verification to be part of the basic design cycle. The design verification methodology presented in this paper represents a minimum scheduled savings of 75% for an LSI machine as compared to any conventional type of design system. It allows the computer industry to design timely systems in the range of one-million circuits and to design them with a cost-effective design system. In addition to savings in schedule, the system described guarantees a high quality design with minimum impact on customer satisfaction because of design errors. The range of effectiveness that can be obtained on a product using this methodology is from 85-95% effective.