Title :
Verification Testing
Author_Institution :
Stanford University, Stanford, CA
Abstract :
A new approach to test pattern generation which is particularly suitable for self-test is described. Required computation time is much less than for present-day automatic test pattern generation (ATPG) programs. Fault simulation is not required. More patterns may be obtained than from standard ATPG programs. However, fault coverage is much higher - all irredundant multiple as well as single stuck faults are detected. Test length is easily controlled. The test patterns are easily generated algorithmically either by program or hardware.
Keywords :
Automatic test pattern generation; Circuit faults; Circuit testing; Computational efficiency; Computer networks; Costs; Fault detection; Laboratories; Test pattern generators; Very large scale integration;
Conference_Titel :
Design Automation, 1982. 19th Conference on
Conference_Location :
Las Vegas, NV, USA
Print_ISBN :
0-89791-020-6
DOI :
10.1109/DAC.1982.1585544
