Title :
Timing Verification System Based on Delay Time Hierarchical Nature
Author :
Nomura, Minoru ; Sato, Shinichi ; Takano, Nobuo ; Aoyama, Toshinori ; Yamada, Akihiko
Author_Institution :
Nippon Electric Co., Ltd., Tokyo, JAPAN
Abstract :
A hierarchical timing verification system is described. It can evaluate all logical paths in a chip without any specific manual input information, using a path tracing algorithm. This hierarchical approach can drastically reduce the number of logical paths to be traced and the corresponding computation time. This system is used for designing master slice (gate array) LSIs and building block LSIs.
Keywords :
Analytical models; Circuit simulation; Cities and towns; Computational modeling; Delay effects; Delay systems; Digital circuits; Fabrication; SPICE; Timing;
Conference_Titel :
Design Automation, 1982. 19th Conference on
Conference_Location :
Las Vegas, NV, USA
Print_ISBN :
0-89791-020-6
DOI :
10.1109/DAC.1982.1585561
