Logic Simulation for LSI

This paper describes the logic simulation system and the design verification method for logic design, timing analysis, and testing for VLSI. The integrity of test and network data on a logic design stage must be kept in LSI testing in the final verification stage. In dealing with consistency, emphasis is placed on the discrepancy between the real time domain on a simulator and a testing time domain on an LSI tester. The logic simulation system (Block INtegrator and AnaLYzer: BINALY) handles a hierarchical structure, a detailed timing model, and a timing alignment method for a testing time domain.