Concurrent techniques for developing motion video compression algorithms

Summary form only given. The authors discuss parallel techniques for speeding up software simulations of video codec algorithms on a reconfigurable MIMD machine with distributed memory (multicomputer). The Edinburgh Concurrent Supercomputer, houses over 400 INMOS T800 transputer floating point microprocessors. Instead of a pipeline, the use of compact graphs in conjunction with an optimised software routing harness is advocated. They can considerably ease the development of concurrent image processing software and provide results better than those obtained from specifically tailored topologies and software. This technique scales to any number of processors with minimal effort